PCI Express Dual Mode Cores
ASIC Architect's high performance cores come in multiple datapath flavors with the choice of 8-bit or 16-bit PIPE PHY Interface. The cores have been architected to achieve very low latency, high throughput, and quick timing closure with a very small silicon footprint. The user interface provides practical and integration-friendly mechanisms for the integration of the cores to the user logic. Our PCI Express products support the most advanced features - Power Management, QoS, Hot-Plug & Hot-Swap, Data Integrity, Trusted Integration and Error Handling.
Block Diagram
Product Overview
- PCI Express Specification 1.1a and 2.0 Compliant (Gen1/Gen 2)
- Highly Scalable & Pipelined Architecture
- High Performance with Low Latency, Maximum Throughput, Multiple Pipelined Memory WR/RD capability
- Low Silicon Footprint - Suitable for Multiple Instances of the Core in Single ASIC/FPGA
- Optimized architecture with multiple datapath widths
- Technology independent design for ASIC/FPGA
- IP Solution Cores built around the PCIe Core provide bridging to AMBA 3 AXI, AMBA 2 AHB, SATA I/II Device/Host, DDR I/II/III interfaces
Click here to download the datasheet
Feature Highlights
- Highly Parameterized Core supporting both cut-through and store-and-forward schemes
- Supports operation with 8-bit and 16-bit PIPE interface
- Implements all optional configuration space and capability structures
- Configurable Retry buffering scheme for low footprint and latency
- Supports all power management states L0, L0s, L1, L2 & L3
- Supports PCI Express Advanced Error Reporting
- Configurable Type-0 (Endpoint) or Type-1 (Root Port,Switch Port) Config Headers
- User configurable Virtual Channels and Traffic Class mapping
Reliability
- Silicon Proven Design
- Design for Testability and Design for Debugability
- Controllability for critical device parameters
- Added in the PCI-SIG PCI Express Integrators List
- Thoroughly verified against industry leading PCI Express verification suites
- Extensive list of Interoperable PCI Express vendors
High Performance
- Supports upto 8 Virtual Channels and 8 Traffic Classes
- Full Isochronous Traffic Support with multiple pipelined Memory Read Capability
- Highly Configurable Retry buffer design for low latency and area depending on user application
- Pipelined/Streaming Operation for Memory Write Requests
- Very Low Transmit and Receive Latency
- Non-Blocking Architecture allows maximum link utilization
- Supports multifunction endpoints
Power Management Features
- Supports all required and optional PCI Express Power Management features
- Supports Beacon and Wake-Up mechanism
- Supports all PM states L0, L0s, L1, L2 & L3
- ClkREQ mechanism for low power mode in mobile form factors
Datapath flavors for PCI Express Cores
| Product Code | Lanes | Datapath |
|---|---|---|
| AA 1101 | x8 Core | 128/64 bit |
| AA 1102 | x4 Core | 128/64/32 bit |
| AA 1103 | x2 Core | 128/64/32 bit |
| AA 1104 | x1 Core | 128/64/32 bit |
| AA 1105 | x16 Core | 128-bit |