PCIe AMBA® 3 AXI Bridge Cores

The design challenges are greatly increased when a bridge is needed between two sophisticated buses such as PCIe and AMBA bus. To overcome these challenges, we have created the PCIe to AMBA® 3 AXI^TM interface bridge product that provides end-to-end connectivity between AMBA 3 AXI bus to PIPE-compliant PCI Express PHY.
Our solution is highly configurable with great flexibility to meet the optimal performance requirements demanded by silicon designers. In addition, it supports the most advanced features in PCI Express - Power Management, QoS, Hot-Plug, Hot-Swap, Error Handling, and it is compliant to AMBA 3 AXI Protocol 1.0 specification and PCI Express specification 1.1.and 2.0.

Block Diagram

Product Overview

• PCI Express Specification 1.1a and 2.0 Compliant (Gen1/Gen 2)
• Low Latency and High Throughput Architecture
• Choice of either Root Mode or Endpoint Mode for PCI Express at Power-up
• Supports MSI or Legacy Interrupt for PCI Express
• Supports system interrupt for ARM or Internal processor
• Supports EEPROM controller to boot load data through SPI Interface
• Support Mailbox between PCI Express and AMBA 3 AXI Bus
• Supports Error Handling of both PCIe and AXI Protocols
• Technology independent design for ASIC/FPGA

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Flexible Addressing and Datawidth

• Supports both 32b/64b addressing from PCIe to AXI bus
• Configurable AMBA Databus - Master and Slave independently configurable to either 32bit or 64bit
• User selectable 5 variable windows from AMBA to PCIe address translations
• User selectable 4 variable windows from PCIe to AMBA address translations
• Up to 4 Base Address Registers (BARs) available in root mode address translation

High Performance

• High throughput with support for 4 outstanding AXI to PCIe memory read transactions
• Handles out-of-order read-completions from PCIe targets
• Supports 1st Party DMA with ability to accept DMA Memory WR/RD commands from PCIe and AMBA Master
• Multiple descriptors per DMA channels
• Local CPU Offload Support through Concurrent DMA WR/RD

Power Management

• Designed for low power application
• Supports all required and optional PCI Express power management states: L0, L0s, L1, L2 & L3
• ClkReq mechanism for low power mode in mobile form factors
• Supports Beacon and Wake-Up mechanism on PCIe Link
• Dedicated Bridge internal registers in PCIe clock domain for software accesiblility during internal power save

Parameterized Design

• Highly Parameterized RTL for easy configurability depending on your custom requirements
• Supports both Cut-Through and Store-and-Forward schemes for forwarding transmitted packets
• User configurable Virtual Channels and Traffic Class mapping
• Selectable ECRC and Advanced Error Reporting Support

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