DDR Memory Controller Cores
ASIC Architect's DDR I/II/III Controller Cores are an integral part of the product portfolio aimed at providing a complete end-to-end solution in the High Speed Interface Controller domain. The DDR controller cores have been architected, designed and verified by ASIC/SoC industry veterans. The add-on solution cores that come with the DDR Controller accelerate the chip-level integration by connecting multiple clients to the DDR Controller. The DDR controller core handles all complex functional aspects of controlling a DDR SDRAM for initializing the memory devices, translating the read and write requests from the application interface into the standard SDRAM command signals, performing ECC for the memory banks. It also provides a powerful application interface to handle multiple application clients with an agent ID based mechanism to route read-completion data to application clients.
Block Diagram
Brief Product Overview
- DDR Controller Cores support DDR I/II/III JEDEC Standards
- Supports Mobile DDR Standards
- 16-Agent Intelligent Arbitration Scheme based on: Priority, Credits, Bank and Aging
- Powerful and Flexible Application Interface with configurable Command and Data FIFOs
- Flexible PHY interface allows to connect to SATA and SAPIS phy interface
- Supports Buffered and Un-Buffered DIMMs
- High data rate upto 100% memory throughput
Click here to download the datasheet
Configurable/Programmable Features
- Programmable Support for DDR 3 Specific Features: MPR,ZQ Calibration and Write Leveling
- Programmable Features include controlling Tras, Trdl, Twr, Tccd, Trfc, Tmrd, Trp, Tcrd and Auto-Refresh interval
- Address Mapping between application bus and row, column & bank address
- Choice of 16/32/64-bit DDR bus-width
- Size of Command Queue
- Supports addition CAS latency feature to maximize command bus utilization
Features Highlights
- Intelligent Bank Management for ensuring maximum utilization and efficiency
- Address Mapping between application bus and row, column & bank address
- Choice of 16/32/64-bit DDR bus-width
- Supports Back-to-Back WR & RD with minimum time intervals
- Supports On-die termination (ODT), and Off-Chip Driver impedance adjustment
- Byte-wide mask support
- Optional ECC support
- Auto initialization of DDR Memories
- Power down control
- Command queuing to maximize the performance on DDR bus
- Fully ATPG Testable - Multiple Clock Domains – Application Clock and DDR Clock
- Supports upto 800MHz in DDR 2 Mode & upto 1.6GHz in DDR 3 Mode
- Low gate count and Low latency
- Verified with leading memory and IO vendors
DDR Controller Product Codes
| Product Code | Description |
|---|---|
| AA 8801 | DDR I Controller Core |
| AA 8801 | DDR II Controller Core |
| AA 8801 | DDR III Controller Core |