July 28th, 2008: Gennum Corporation (TSX: GND) today announced it has acquired ASIC Architect, Inc., a leading developer of high-speed controller intellectual property (IP) based in Santa Clara, California. This acquisition accelerates Gennum's new analog and mixed-signal product introductions and complements its existing Snowbush IP offering, which currently consists of advanced physical layer (PHY) IP cores for high-speed data communications. ...read more

Apr 28th, 2008: ASIC Architect, Inc. today announced the availability of Multi-Port Intelligent Arbiter and Scheduler (MPIAS) with optional AMBA 3 AXI or AMBA 2 AHB Interface for it successful DDR Controller Cores. This follows the footsteps of company's highly successful industry-leading controllers in the area of PCI Express, DDR and SATA...read more

ASIC Architect, Inc. today announced the availability of DDR 3 Controller Cores. The DDR 3 Controller Core supports JEDEC's DDR 3 DRAM architecture. The DDR 3 Controller core combined with the newly released Multi-Port Intelligent Arbiter and Scheduler (MPIAS) Core provides a winning solution for the high-end ASIC/SoC customers looking for high performance measured by low latency, low power, high throughput, QOS, and fairness control...read more

ASIC Architect, Inc. today announced the availability of PCI Express Gen 2 Controller Cores - in multiple lane width configurations - x16, x8, x4, x1. This follows the footsteps of company's highly successful industry-leading PCI Express Gen 1 Controller Cores. The product is developed based on PCI Express Specification 2.0 and is backward compatible with PCI Express Specification 1.1 ...read more

Phylinks, Inc., an innovator of IP cores for the design of physical layer (PHY) high-speed serial interfaces, announced today that it has delivered working-first-silicon of its PHY-820 PCIe PHY at the .13u process technology node. The PHY is designed with Phylinks' robust design-for-test (DFT) architecture with an extremely small footprint and low power consumption ...read more

Mentor Graphics Corporation today announced availability of PCI Express® (PCIe® Controller and AMBA® Bridge intellectual property (IP) solutions for the rapid and cost-effective integration into ASIC and System-On-Chip (SoC) platforms. Featuring a complete suite of PCIe Controllers, including X1 (1-lane), X2 (2-lane), X4 (4-lane), X8 (8-lane) and X16 (16-lane) options, the solutions also include AMBA 3 AXI(TM) and AMBA 2 AHB(TM) Bridges to standard on-chip buses...read more

ASIC Architect, Inc. today announced the availability of AMBA® 2 AHB^TM to PCI Express bridge product for PCI Express controllers. The solution product has passed PCI Express Compliance and Interoperability testing in PCI-SIG compliance workshop. This solution enables SoC designers to plug-in PCI Express Controller Core into AMBA 2 AHB system bus. This directly leads to low design implementation risk...read more

Averant Inc, a leading provider of advanced verification technology for RTL designs, today announced the achievement of AMBA(R) 3 Assured status for SolidPC(TM) 2.0, Averant's property checking product for AMBA interconnect protocol compliance ...read more

ASIC Architect, Inc. today announced the expansion of its operation at Bhubaneswar, the capital city of Orissa, India, approximately 890 miles from the city of Bangalore. The company moved to a central location in Forest Park, a few minutes from Bhubaneswar airport. The company started its India operation in June 2006 and recently moved to this expanded location to accommodate future growth...read more

eASIC Corporation, a provider of Structured ASIC devices and Configurable logic IP, and ASIC Architect, a leading supplier of high speed IP cores, today announced the immediate availability of two new high-speed interfaces for eASIC's 90nm Nextreme Structured ASIC Family: PCI Express (PCIe) Endpoint Controller and DDR2 memory controller. The PCIe controller features maximum data throughput with a latency of less than 11 clock cycles and provides local connectivity for, wireless, desktop, enterprise and communications system platforms. The DDR2 core is tuned to provide connectivity to the latest DDR2 memories at speeds up to 533MHz. Both PCI Express and DDR2 Controllers have been hardware proven in eASIC's Nextreme Structured ASICs devices ...read more

ASIC Architect, Inc. today announced the availability of Configurable AMBA® 3 AXI^TM Bridge IP for its DDR Controller Cores. This solution will enable SoC designers to plug-in DDR Controller Core into AMBA 3 AXI system bus, and mitigate the implementation risk and time-to-market challenges...read more

ASIC Architect, Inc. today announced the availability of Configurable AMBA® 3 AXI^TM Bridge IP for its PCI Express Controller Cores. This solution will enable SoC designers to plug-in PCI Express Controller Core into AMBA 3 AXI system bus, and mitigate the implementation risk and time-to-market challenges...read more

Avery Design Systems and ASIC Architect today announced a cooperative effort to deliver a comprehensive Serial ATA (SATA) design and verification IP solution...read more